CD74HC109EE4 | High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset | Datasheet*) |
CD74HC109M96E4 | High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset | Datasheet*) |
CD74HC109ME4 | High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset | Datasheet*) |
CD74HC109MTE4 | High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset | Datasheet*) |
CD74HCT109EE4 | High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset | Datasheet*) |
CD74HCT109M96E4 | High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset | Datasheet*) |
CD74HCT109ME4 | High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset | Datasheet*) |
CD74HCT109MTE4 | High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset | Datasheet*) |