| CD54HC107F3A | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE TRIGGER J-K FLIP-FLOPS WITH RESET in 14-pin J package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
| CD74HC107E | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET in 14-pin N package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
| CD74HC107M | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET in 14-pin D package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
| CD74HC107M96 | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET in 14-pin D package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
| CD74HCT107E | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET in 14-pin N package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
| 5962-9070101MEA | HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE TRIGGER J-K FLIP-FLOPS WITH SET AND RESET in 16-pin J package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
| CD54HC109F3A | HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE TRIGGER J-K FLIP-FLOPS WITH SET AND RESET in 16-pin J package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
| CD54HCT109F3A | HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE TRIGGER J-K FLIP-FLOPS WITH SET AND RESET in 16-pin J package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
| CD74HC109E | HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET in 16-pin N package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
| CD74HC109M | HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET in 16-pin D package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
| CD74HC109M96 | HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET in 16-pin D package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
| CD74HCT109E | HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET in 16-pin N package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
| CD74HCT109M | HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET in 16-pin D package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
| CD74HCT109M96 | HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET in 16-pin D package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
| CD54HC10F | HIGH SPEED CMOS LOGIC TRIPLE 3-INPUT NAND GATES in 14-pin J package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
| CD54HC10F3A | HIGH SPEED CMOS LOGIC TRIPLE 3-INPUT NAND GATES in 14-pin J package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
| CD54HCT10F3A | HIGH SPEED CMOS LOGIC TRIPLE 3-INPUT NAND GATES in 14-pin J package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
| CD74HC10E | HIGH SPEED CMOS LOGIC TRIPLE 3-INPUT NAND GATES in 14-pin N package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
| CD74HC10M | HIGH SPEED CMOS LOGIC TRIPLE 3-INPUT NAND GATES in 14-pin D package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
| CD74HC10M96 | HIGH SPEED CMOS LOGIC TRIPLE 3-INPUT NAND GATES in 14-pin D package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
| CD74HCT10E | HIGH SPEED CMOS LOGIC TRIPLE 3-INPUT NAND GATES in 14-pin N package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
| CD74HCT10M | HIGH SPEED CMOS LOGIC TRIPLE 3-INPUT NAND GATES in 14-pin D package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
| CD74HCT10M96 | HIGH SPEED CMOS LOGIC TRIPLE 3-INPUT NAND GATES in 14-pin D package. Operational temperature range from -55°C to 125°C. | Datasheet*) |
| 5962-8984301CA | High-Speed CMOS Logic Triple 3-Input NAND Gate | Datasheet*) |
| CD54HC10 | High-Speed CMOS Logic Triple 3-Input NAND Gate | Datasheet*) |
| CD54HCT10 | High-Speed CMOS Logic Triple 3-Input NAND Gate | Datasheet*) |
| CD74HC10MT | High-Speed CMOS Logic Triple 3-Input NAND Gate | Datasheet*) |
| CD74HCT10MT | High-Speed CMOS Logic Triple 3-Input NAND Gate | Datasheet*) |
| CD54HC107 | Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Datasheet*) |
| CD74HC107MT | Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Datasheet*) |
| CD54HC109 | Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger | Datasheet*) |
| CD54HCT109 | Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger | Datasheet*) |
| CD74HC109MT | Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger | Datasheet*) |
| CD74HCT109MT | Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger | Datasheet*) |
